Modelling of nano nMOSFETs with alternative channel materials in the fully and quasi ballistic regimes

Birth, growth and challenges of the semiconductor industry 

Birth of the semiconductor industry

A careful look at the history of the birth of the semiconductor industry  shows that nearly 10 years of intense research on solid-state physics at the Bell Telephone Laboratory have been necessary for John Bardeen, Walter Brattain and William Shockley to fabricate the first transistor in December 1947. This transistor, was a point contact one. It was based on the current modulation of a germanium diode by the injection of holes from a third contact. Quickly following this invention, germanium point contact transistors have been industrially produced and commercialized. Soon after, the point contact architecture has been replaced by the bipolar one, still using germanium as semiconductor material.

Despite its high carrier mobilities, the use of germanium has however always been an issue, principally due to its small energy bandgap (0.66eV at room temperature), which makes these devices thermally instable: Ge becomes intrinsic at not so high temperature (because of the transistor self heating, but most generally because of the environment), which eliminates the distinction between the p and n-doped region thus causing failure of device operation. The germanium based transistors were therefore replaced within few years by bipolar silicon transistors, which presented higher thermal stability thanks to the larger silicon energy bandgap.

Later, in the beginning of the 60s, further developments at the Bell Labs in crystal growth, silicon oxidation and doping techniques lead to the fabrication of the first Metal Oxide Semiconductor Field Effect Transistor (MOSFET). At the same period, the first integrated circuit was invented and fabricated by Texas Instrument and Fairchild Semiconductor.

The combination of these two winning strategies, i.e. the use of integrated circuit with silicon MOSFETs, gave birth to one of the most significant industrial revolutions of the XXth century.

The silicon MOSFET, technical key of a success 

One of the main technical origins of the success of the semiconductor industry is undeniably the use of silicon Metal Oxide Semiconductor Field Effects Transistors as core device.

For digital application, which is the main produced and commercialized technology, silicon MOSFET is clearly superior to other transistors thanks to:
• Its cost effectiveness, resulting from the planar process involved in its fabrication and the abundance of silicon (roughly 25% of earth’s crust) ;
• Its stable oxide layer, not obtainable from other semiconductors, enabling a low power shift from off to on state ;
• The possibility to obtain nearly ideal complementary MOS switches thanks to nand p-type devices with quite well balanced characteristics
• Its increase of performance when properly scaled.

The last point is particularly relevant since the performance enhancement and the increase of devices density enabled by MOSFET scaling has been – and is still – the key challenge for the semiconductor industry: increasing the device density allowed the design of more and more complex functions and reduced drastically the cost of a single transistor . In parallel, the ICs global performances have been increased (higher frequency) and the total power consumption can be reduced (same performance at lower voltage). This ability of the MOSFET to present higher performances while scaled down allowed a fast and steady growth of the semiconductor industry for almost 40 years.

End of the « Happy scaling » era 

The scaling rules have been successfully applied during the 70s and the 80s, called the “Happy scaling” era, enabling a constant growth of the semiconductor industry. However, many physical limitations were foreseen to stop it. In the 80s, the submicronic scale was expected to lead to too high Short Channel Effect , and strong channel hot electron injection degrading the device stable operation in the long term. In the 90s, when the gate lengths were reaching half a micron, high access resistances were likely to lead to significant performance degradation. Finally, when the gate lengths reached 250nm, tunneling current through the oxide was foreseen as possible breakdown sources.

However technological solutions have been found in each case to avoid these limitations. Short Channel Effects are reduced thanks to engineered source, drain and channel doping profiles (lightly doped drain [OgurTED80] and pocket implants [WannTED96]), salicide source drain [IwaiMicEng02] are used to reduce parasitic access resistances and gate tunneling leakage is avoided thanks to the recent industrial introduction of higk-κ dielectrics [GuseMicEng01].

Nevertheless, new limitations are arising since the transistor gate length is expected to be scaled down to 7nm in 2018 [ITRS2007], partly due to the intrinsic physical limitation of silicon as a channel material. In addition, the former parasitic effects are also strengthened as devices continue to scale down. Therefore, new solutions are required to face these new technological challenges.

Forthcoming challenges for the semiconductor industry 

Aside from many new technological issues (red brick wall of the ITRS [ITRS2007]), one of the major forthcoming challenges for the semiconductor industry deals with carrier transport limitations in silicon channels. Indeed, as the channel length now reached the decananometer scale, the impact of carrier scattering is becoming weaker [PaleTED05], whereas they were predominant at larger scale. Carrier transport thus enters a transition from close-to-equilibrium transport to strong non equilibrium transport regime. All former transport model assuming close-to equilibrium conditions, like Drift Diffusion transport models, are therefore not valid anymore and in addition, the concepts of mobility and velocity saturation become also questionable.

This far from equilibrium transport regime expected to occur in ultra short devices has been widely studied since the mid-90s. In particular, detailed studies of carrier transport in decananometer channels thanks to Monte Carlo simulation [PaleTED05] showed that, due to the weaker influence of scattering on carrier transport, a significant proportion of electrons can be emitted by the source to reach the drain without suffering any scattering. These electrons are thus ballistic.

When transport combines scattered and non-scattered (ballistic) carriers in comparable fractions, the transport regime is called quasi-ballistic, which is in essence a complex transition from long channel to ultra-short channel transport. It is also expected that fully ballistic transport, i.e. governed by non scattered electrons only, will occur in ultra-scaled devices (i.e. for channel length around 10nm for silicon).

Table des matières

Chapter 1 : Introduction
1.1 Context : why alternative channel materials ?
1.1.1 Birth, growth and challenges of the semiconductor industry
1.1.1.1 Birth of the semiconductor industry
1.1.1.2 The silicon MOSFET, technical key of a success
1.1.1.3 End of the « Happy scaling » era
1.1.2 Forthcoming challenges for the semiconductor industry
1.2 State of the art in the alternative channel material CMOS performance modeling
1.2.1 Literature review
1.2.2 Aim of the thesis
Chapter 2 : Ballistic On current of nano nMOSFETs featuring arbitrarily oriented alternative channel material
2.1 Introduction
2.2 Modelling of the ballistic on state current of arbitrary oriented alternative channel
DGFETs
2.2.1 Carrier transport in the full ballistic regime
2.2.2 The Natori model of full ballistic transport
2.2.3 Generalized Natori model
2.3 Impact of channel material and channel orientation on the on state performance of ultrascaled DGFETs
2.3.1 Impact of channel direction in (100) and (111) substrates
2.3.2 Impact of channel direction in (110) substrates
2.3.2.1 Semiconductors optimum channel orientations on the (110) surface
2.3.2.2 Impact of confinement on Anisotropy
2.3.2.3 Transport in (110) substrate compared to (100) and (111)
2.3.3 Impact of the bandstructure modification in presence of strong quantization: a
literature review
2.4 Conclusion
Chapter 3 : Source-drain leakages in alternative channel material
3.1 Introduction
3.2 Modelling of subthreshold source-drain leakage mechanisms
3.2.1 Impact of source-drain leakage mechanisms on the device performance
3.2.2 Short Channel Effect and Drain Induced Barrier Lowering (SCE and DIBL)
3.2.3 Source to Drain Tunnelling (SDT)
3.2.3.1 Starting equations
3.2.3.2 Transparency calculation
3.2.3.3 Multi-subband channel orientation dependent source-to-drain tunnelling
current model
3.2.3.4 Single subband, channel orientation independent source-to-drain tunnelling
current model
3.2.4 Band to Band Tunnelling (BBT)
3.3 Impact of source-drain leakages on the performances of alternative channel material
nano-MOSFETs
Quentin Rafhay – Modelling of nano nMOSFETs with alternative channel materials
in the fully and quasi ballistic regimes
3.3.1 Comparing channel material
3.3.1.1 Device orientation optimisation
3.3.1.2 Alternative channel material MOSFET performance comparison
3.3.1.3 Conclusions
3.3.2 Role of effective masses and band gaps on the performances of nano
nMOSFETs
3.3.2.1 Models and methodology
3.3.2.2 Results and discussions
3.3.2.3 Conclusions
3.4 Conclusion
Chapter 4 : Scattering and Quasi-Ballistic (QB) transport in alternative channel material nano-nMOSFETs
4.1 Introduction
4.2 The Boltzmann Transport Equation and the Monte Carlo approach
4.2.1 The Boltzmann Transport Equation (BTE)
4.2.2 Monte Carlo (MC) solution of the BTE
4.2.2.1 Principle of Monte Carlo simulations
4.2.2.2 Main inputs of a MC simulator
4.3 Specificities of the Multi Subbands Monte Carlo
4.4 Germanium and gallium-arsenide bulk mobility
4.4.1.1 Bulk crystal mobility solver
4.4.1.2 Mobility calculation using a Multi Subbands Monte Carlo code
4.5 Germanium inversion layer mobility
4.5.1 The nMOS mobility issue
4.5.2 Monte Carlo simulation study
4.5.3 Inversion layer mobility in Germanium On Insulator (GeOI) nMOSFET
4.6 Quasi Ballistic transport in Ge DGFETs
4.6.1 The Lundstrom model of quasi-ballistic transport
4.6.2 Monte Carlo simulations of backscattering in Ge DGFETs
4.6.3 Results and discussion
4.7 Conclusions
Chapter 5 : Conclusion

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