Soutenance mémoire
Ferroelectric FET
The Ferroelectric Field Effect Transistor (FeFET) memory is a 1T memory device where a ferroelectric capacitor is integrated into the gate stack of a FET. The ferroelectric polarization directly affects charges in the channel and leads to a defined shift of the output characteristics of the FET. A typical FeFET memory element uses inorganic complex oxides or fluorides, such as PbZrxT i1´xO3, SrBa2Ta2O9, BiMgF4, in the gate stack of a silicon FET. The main difficulty with these materials is interdiffusion and chemical reaction between the stack interfaces at the high deposition temperatures and high oxygen concentrations needed for deposition of the ferroelectric films on a Si substrate [Gerber et al., 2010; Ishiwara, 2009b]. Short retention of the FeFET memory raises question of its potential for application as nonvolatile memory, e.g. for the SCM technologies. Besides, DRAM-like applications are envisioned and the FeFET memory may have a potential for SCM, if scalability below 50nm can be demonstrated. Currently, new materials for the FeFET stacks are being actively investigated, such as organic ferroelectrics [Gerber et al., 2010; Heremans et al., 2011], nanotubes [Fu et al., 2009], nanowires [Sohn et al., 2010], and graphene [Zheng et al., 2011]. The FeFET memory scaling is projected to end approximately with the 22nm generation, due to the fact that the insulation layer becomes too thin and the properties of the ferroelectric, with respect to thickness dependency of the coercive field, will not allow further reduction [Fitsilis, 2005; Fitsilis et al., 2005].
Nanoelectromechanical memory (NEMM)
The Nanoelectromechanical Memory (NEMM) is based on a bi-stable Nanoelectromechanical switch (NEMS). In this concept, mechanical digital signals are represented by displacements of solid nanoelements (e.g. nanowires, nanorods, or nanoparticles),which result in closing or opening of an electrical circuit. Several different modifications of suspended-beam/cantilever NEMMs are currently being explored with different materials, including Si [Ng et al., 2011], Ge [Andzane et al., 2009], T iN [Lee and Choi,2011] and Carbon Nano Tubes (CNT) [Loh et al., 2011]. NEMM scaling analysis [Choi et al., 2008] suggests that it might be difficult to achieve low-voltage („ 1V) operation for the beam length of less than 50nm. Vertically oriented cantilever switches could reduce the NEMM area footprint [Ng et al., 2011]. In addition, nanoelectromechanical torsion switches has recently been demonstrated [Rubin et al., 2011; Xiang and Lee,2010], which are claimed to have better scaling properties [Rubin et al., 2011]. There are also proposals for hybrid NEMS-floating gate memory devices aiming at the improvement of write/erase characteristics. In these devices, either floating gate [Tasuku Nagami et al., 2010] or control gate [Garcia-Ramirez et al., 2010] are built as a suspended bridge or cantilever [Lee et al., 2011b] separated by an air gap. The suspended bridge electrode can move within the gap under applied voltage, thus changing the separation between the control and floating gates, smaller for the fast write/erase and larger for longer retention time for the storage mode. Limited endurance is a serious issue of experimentally demonstrated NEMM devices, as they often fail after „ 100 switching cycles
Redox Memory
The redox-based nanoionic memory operation is based on a change in resistance of a Metal-Insulator-Metal (MIM) structure caused by ion (cation or anion) migration combined with redox processes involving the electrode material or the insulator material, or both [Akinaga and Shima, 2010; Waser et al., 2009]. So far, were identified three classes of electrically induced phenomena that involves chemical effects, which are related to redox processes in the MIM cell. In these three ReRAM classes, there is a competition between thermal and electrochemical driving forces involved in the switching mechanism. The bipolar electrochemical metallization mechanism or memory effect (ECM), relies on an electrochemically active electrode metal, such as Ag. The drift of the highly mobile Ag+ cations in the ion conducting I layer and their electromigration towards the (inert) counter electrode, leads to a growth of Ag dendrites. These dendrites form a highly conductive filament connecting the metal electrodes that results in the ON state of the cell [Valov et al., 2011]. Upon reversal of polarity of the applied voltage, an electrochemical dissolution of these filaments takes place, resetting the system into the high-resistance OFF state. The valence change mechanism (VCM) or memory effect occurs in specific transition metal oxides and is triggered by a migration of anions, such as oxygen anions. A subsequent change of the stoichiometry leads to a redox reaction expressed by a valence change of the cation and a change in the conductivity. This bipolar memory switching is induced by voltage pulses, where the polarity of the pulse determines the direction of the change, i.e. reduction or oxidation. A third class relies on a unipolar The material class for redox memory is comprised of oxides, higher chalcogenides (including glasses), semiconductors, as well as organic compounds including polymers. In some cases, a formation process required before the bi-stable switching can be started [Akinaga and Shima, 2010]. Often, the conduction is of filamentary nature. If this effect can be controlled, memories based on this bi-stable switching process can be scaled to very small feature sizes. The switching speed is limited by the ion transport. If the active distance, which is relevant for the redox controlled bi-stable switching, is small (around ă 10nm) the switching time can be as low as a few nanoseconds. Many details of the mechanism of the phenomena are still unknown. Developing an understanding of the physical mechanisms governing switching of the redox memory is a key aspect for this technology. Recent experimental demonstrations of scalability, retention and endurance seems encouraging, and there is still room for improvements
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Table des matières
i introduction
1 introduction
ii state of the art, drafted methodologies and materials
2 current state of memory technology
2.1 Memory Taxonomy
2.2 Memory Devices
2.2.1 Ferroelectric Memory
2.2.1.1 Ferroelectric FET
2.2.1.2 Ferroelectric Polarization ReRAM
2.2.2 Nanoelectromechanical memory (NEMM)
2.2.3 Redox Memory
2.2.4 Mott Memory
2.2.5 Macromolecular Memory
2.2.6 Molecular Memory
2.2.6.1 Vertical Transistors
2.2.6.2 Two-terminal select devices (resistance-based memories)
2.2.6.3 Diode-type select devices
2.2.7 Resistive-Switch-type select devices
2.2.7.1 MIT switch
2.2.7.2 Threshold switch
2.2.7.3 MIEC switch
2.2.7.4 2 Terminal Switches
2.3 Magnetic Tunneling Junction (MTJ)
2.3.1 Tunnel Magnetoresistance (TMR)
2.3.2 Field Induced Magnetic Switching (FIMS) MRAMs
2.3.3 Thermally Assisted Switching (TAS) MRAMs
2.3.4 Spin Transfer Torque (STT) RAMs
2.3.5 STT based Magnetic Tunnel Junction (STT-MTJ)
2.3.6 Planar and Perpendicular STT
2.4 Current state compared to the memory state of the art
2.5 Computer Architecture and Memory Hierarchy
2.5.1 Working Principles of the Memory Hierarchy
2.6 CACHE Memories
2.6.1 Larger block size to reduce MISS rate
2.6.2 Bigger caches to reduce MISS rate
2.6.3 Higher associativity to reduce MISS rate
2.6.4 Multilevel caches to reduce MISS penalty
2.6.5 Giving priority to read misses over writes to reduce MISS penalty
2.6.6 Avoiding address translation during indexing of the cache to reduce HIT time
2.7 MRAM applied into Memory Hierarchy
3 analytical methodology flow
3.1 CACTI: Integrated Memory Simulator
3.1.1 CACTI background
3.1.2 CACTI Thesaurus
3.1.3 NUCA Modeling
3.2 NVSim
3.2.1 NVSim Non-Volatile Memory (NVM) Physical Mechanisms and Write Operations
3.2.2 NAND Flash
3.2.3 STT-RAM
3.2.4 PCRAM
3.2.5 ReRAM
3.2.6 Charge Pump
3.2.7 Write Endurance Issue
3.2.8 Retention Time Issue
3.2.9 MOS-Accessed Structure Versus Cross-Point Structure
3.3 Comparison of NVSim to CACTI
3.4 Reliability of the methodology base-line models
3.5 Methodology to Evaluate the Intrinsic aspects of MRAM compared to SRAM memories
3.5.1 Memory models used in NVSim for analyses
3.5.2 Intrinsic Analyses
3.5.3 Intrinsic Analyses – Results
3.5.3.1 Memory banks of 45nm
3.6 Methodology to Evaluate the aspects of MRAM into Memory Hierarchy
3.7 SimpleScalar
3.8 Gem5
3.8.1 Simulation Capabilities
3.8.2 ISAs
3.8.3 Execution Modes
3.8.4 CPU Models
3.8.5 Interconnection Networks
3.8.6 Devices
4 analyses of embedded memory hierarchy
4.1 Embedded MRAM for Processor Applications
4.1.1 MRAM applications for the processor memory hierarchy
4.1.2 In-Depth Analysis: Case Study CJPEG
4.2 Using Gem5 to evaluate the implications into memory hierarchy of L2 CACHE banks of significant sizes from 2GB down to 256KB
4.2.1 Recalibrating the Gem5 using the NVSim bank details
4.2.2 Power Analysis based into the memory banks generated after the NVSim
4.3 Benchmarks used for evaluations
4.4 Comparing a Microprocessor memory hierarchy, synthesized with MRAM and SRAM at 28nm
4.4.1 OpenRISC Architecture
4.4.1.1 Memory Model
4.4.1.2 Memory Synchronize Instruction
4.4.1.3 Memory Management
4.4.2 MRAM Characterization using Liberty
4.4.3 Synthesis Results
4.4.4 MRAM and Static Random Access Memory (SRAM) synthesis results
4.4.5 Assessments comparing the synthesis results of the two technolgies
4.5 The Composite Bank
4.5.1 Composite Memory banks of 45nm
5 conclusions & future insights
vi appendix
a mram terminology
a.1 Anisotropy
a.2 Magnetic anisotropy
a.3 Superparamagnetism
a.4 Magnetic Permeability
a.5 Isotropy
a.6 Magnetic moment
a.7 Magnetic moment and angular momentum
a.8 Exchange bias
a.9 Antiferromagnetism
a.9.1 Measurement
a.9.2 Antiferromagnetic materials
a.9.3 Geometric frustration
b improving the reliability of a fpga using fault-tolerance mechanism based on mram
b.1 Reliability
b.2 Mechanism to improve reliability regarding SEU events
b.3 Scrubbing Mechanism – Refresh the configuration bits
b.4 General approach
b.5 Error Detection Code
b.6 Experimental Results
b.7 Hamming results
b.8 BCH Results
b.9 Assessments on MRAM applied to FPGA to improve reliability
c intrinsic analyses – additional results
d cacti analytical models – relevant details
d.1 CACTI Analytical Models
d.2 Wire Parasitics
d.3 Global Wires
d.4 Low-swing Wires
d.5 Transmitter
d.6 Sense Amplifier
e intrinsic analyses – memory banks of 28nm
f the composite bank – additional results
f.1 LOP 45nm
f.2 Composite Baank 28nm
f.3 LOP 28nm
bibliography
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